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? semiconductor components industries, llc, 2012 october, 2012 ? rev. 0 1 publication order number: cat25m01/d cat25m01 1 mb spi serial cmos eeprom description the cat25m01 is a 1m ? bit serial cmos eeprom device internally organized as 128kx8 bits. this features a 256 ? byte page write buffer and supports the serial peripheral interface (spi) protocol. the device is enabled through a chip select (cs ) input. in addition, the required bus signals are clock input (sck), data input (si) and data output (so) lines. the hold input may be used to pause any serial communication with the cat25m01 device. the device features software and hardware write protection, including partial as well as full array protection. on ? chip ecc (error correction code) makes the device suitable for high reliability applications. features ? 10 mhz spi compatible ? 1.8 v to 5.5 v supply voltage range ? spi modes (0,0) & (1,1) ? 256 ? byte page write buffer ? additional identification page with permanent write protection ? self ? timed write cycle ? hardware and software protection ? block write protection ? protect 1/4, 1/2 or entire eeprom array ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? industrial and extended temperature range ? 8 lead soic and tssop packages ? this device is pb ? free, halogen free/bfr free and is rohs compliant figure 1. functional symbol so v ss cat25m01 v cc si cs wp hold sck http://onsemi.com see detailed ordering and shipping information in the package dimensions section on p age 14 of this data sheet. ordering information pin configuration si hold v cc v ss wp so cs 1 sck soic (v, x), tssop (y) (top view) chip select cs serial data output so write protect wp ground v ss serial data input si serial clock sck function pin name pin function hold transmission input hold power supply v cc soic ? 8 v suffix case 751bd tssop ? 8 y suffix case 948al soic ? 8 x suffix case 751be
cat25m01 http://onsemi.com 2 table 1. absolute maximum ratings parameter ratings units operating temperature ? 45 to +130 c storage temperature ? 65 to +150 c voltage on any pin with respect to ground (note 1) ? 0.5 to +6.5 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the dc input voltage on any pin should not be lower than ? 0.5 v or higher than v cc + 0.5 v. during transitions, the voltage on any pin may undershoot to no less than ? 1.5 v or overshoot to no more than v cc + 1.5 v, for periods of less than 20 ns. table 2. reliability characteristics (note 2) symbol parameter min units n end (note 3) endurance 1,000,000 program / erase cycles t dr data retention 100 years 2. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. 3. page mode, v cc = 5 v, 25 c 4. the device uses ecc (error correction code) logic with 6 ecc bits to correct one bit error in 4 data bytes. therefore, when a single byte has to be written, 4 bytes (including the ecc bits) are re ? programmed. it is recommended to write by multiple of 4 bytes in order to benefit from the maximum number of write cycles. table 3. d. c. operating characteristics (v cc = 1.8 v to 5.5 v, t a = ? 40 c to +85 c and v cc = 2.5 v to 5.5 v, t a = ? 40 c to +125 c, unless otherwise specified) symbol parameter test conditions min max units i ccr supply current (read mode) read, so open / ? 40 c to +85 c v cc = 1.8 v, f sck = 5 mhz 1.2 ma v cc = 2.5 v, f sck = 10 mhz 1.8 ma v cc = 5.5 v, f sck = 10 mhz 3 ma read, so open / ? 40 c to +125 c 2.5 v < v cc < 5.5 v, f sck = 10 mhz 3 ma i ccw supply current (write mode) write, cs = v cc / ? 40 c to +85 c 1.8 v < v cc < 5.5 v 3 ma write, cs = v cc / ? 40 c to +125 c 2.5 v < v cc < 5.5 v 3 ma i sb1 standby current v in = gnd or v cc , cs = v cc , wp = v cc , hold = v cc , v cc = 5.5 v t a = ? 40 c to +85 c 1 a t a = ? 40 c to +125 c 3 i sb2 standby current v in = gnd or v cc , cs = v cc , wp = gnd, hold = gnd, v cc = 5.5 v t a = ? 40 c to +85 c 3 a t a = ? 40 c to +125 c 5 a i l input leakage current v in = gnd or v cc ? 2 2 a i lo output leakage current cs = v cc v out = gnd or v cc ? 2 2 a v il1 input low voltage v cc 2.5 v ? 0.5 0.3v cc v v ih1 input high voltage v cc 2.5 v 0.7v cc v cc + 0.5 v v il2 input low voltage v cc < 2.5 v ? 0.5 0.25v cc v v ih2 input high voltage v cc < 2.5 v 0.75v cc v cc + 0.5 v v ol1 output low voltage v cc 2.5 v, i ol = 3.0 ma 0.4 v v oh1 output high voltage v cc 2.5 v, i oh = ? 1.6 ma v cc ? 0.8v v v ol2 output low voltage v cc < 2.5 v, i ol = 150 a 0.2 v v oh2 output high voltage v cc < 2.5 v, i oh = ? 100 a v cc ? 0.2v v
cat25m01 http://onsemi.com 3 table 4. pin capacitance (t a = 25 c, f = 1.0 mhz, v cc = +5.0 v) (note 5) symbol test conditions min typ max units c out output capacitance (so) v out = 0 v 8 pf c in input capacitance (cs , sck, si, wp , hold ) v in = 0 v 8 pf 5. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. table 5. a.c. characteristics (t a = ? 40 c to +125 c, unless otherwise specified.) (note 6) symbol parameter v cc = 1.8 v ? 5.5 v ? 40 c to +85 c v cc = 2.5 v ? 5.5 v ? 40 c to +125 c units min max min max f sck clock frequency dc 5 dc 10 mhz t su data setup time 20 10 ns t h data hold time 20 10 ns t wh sck high time 75 40 ns t wl sck low time 75 40 ns t lz hold to output low z 50 25 ns t ri (note 8) input rise time 2 2 s t fi (note 8) input fall time 2 2 s t hd hold setup time 0 0 ns t cd hold hold time 10 10 ns t v output valid from clock low 75 40 ns t ho output hold time 0 0 ns t dis output disable time 50 20 ns t hz hold to output high z 100 25 ns t cs cs high time 80 40 ns t css cs setup time 60 30 ns t csh cs hold time 60 30 ns t cns cs inactive setup time 60 30 t cnh cs inactive hold time 60 30 t wps wp setup time 10 10 ns t wph wp hold time 10 10 ns t wc (note 7) write cycle time 5 5 ms 6. ac test conditions: input pulse voltages: 0.3 v cc to 0.7 v cc input rise and fall times: 10 ns input and output reference voltages: 0.5 v cc output load: current source i ol max /i oh max ; c l = 30 pf 7. t wc is the time from the rising edge of cs after a valid write sequence to the end of the internal write cycle. table 6. power ? up timing (notes 8 and 9) symbol parameter max units t pur power ? up to read operation 1 ms t puw power ? up to write operation 1 ms 8. this parameter is tested initially and after a design or process change that affects the parameter. 9. t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated.
cat25m01 http://onsemi.com 4 pin description si: the serial data input pin accepts op ? codes, addresses and data. in spi modes (0,0) and (1,1) input data is latched on the rising edge of the sck clock input. so: the serial data output pin is used to transfer data out of the device. in spi modes (0,0) and (1,1) data is shifted out on the falling edge of the sck clock. sck: the serial clock input pin accepts the clock provided by the host and used for synchronizing communication between host and cat25m01. cs : the chip select input pin is used to enable/disable the cat25m01. when cs is high, the so output is tri ? stated (high impedance) and the device is in standby mode (unless an internal write operation is in progress). every communication session between host and cat25m01 must be preceded by a high to low transition and concluded with a low to high transition of the cs input. wp : the write protect input pin will allow all write operations to the device when held high. when wp pin is tied low and the wpen bit in the status register (refer to status register description, later in this data sheet) is set to ?1?, writing to the status register is disabled. hold : the hold input pin is used to pause transmission between host and ca t25m01, without having to retransmit the entire sequence at a later time. to pause, hold must be taken low and to resume it must be taken back high, with the sck input low during both transitions. when not used for pausing, it is recommended the hold input to be tied to v cc , either directly or through a resistor. functional description the cat25m01 device supports the serial peripheral interface (spi) bus protocol, modes (0,0) and (1,1). the device contains an 8 ? bit instruction register. the instruction set and associated op ? codes are listed in table 7. reading data stored in the ca t25m01 is accomplished by simply providing the read command and an address. writing to the cat25m01, in addition to a write command, address and data, also requires enabling the device for writing by first setting certain bits in a status register, as will be explained later. after a high to low transition on the cs input pin, the cat25m01 will accept any one of the six instruction op ? codes listed in table 7 and will ignore all other possible 8 ? bit combinations. the communication protocol follows the timing from figure 2. the cat25m01 features an additional identification page (256 bytes) which can be accessed for read and write operations when the ipl bit from the status register is set to ?1?. the user can also choose to make the identification page permanent write protected. table 7. instruction set instruction opcode operation wren 0000 0110 enable write operations wrdi 0000 0100 disable write operations rdsr 0000 0101 read status register wrsr 0000 0001 write status register read 0000 0011 read data from memory write 0000 0010 write data to memory figure 2. synchronous data timing sck si so hi ? z valid in valid out hi ? z cs t cnh t css t wh t wl t h t su t ri t fi t v t v t ho t csh t cs t cns t dis
cat25m01 http://onsemi.com 5 status register the status register, as shown in table 8, contains a number of status and control bits. the rdy (ready) bit indicates whether the device is busy with a write operation. this bit is automatically set to 1 during an internal write cycle, and reset to 0 when the device is ready to accept commands. for the host, this bit is read only. the wel (write enable latch) bit is set/reset by the wren/wrdi commands. when set to 1, the device is in a write enable state and when set to 0, the device is in a w rite disable state. the bp0 and bp1 (block protect) bits determine which blocks are currently write protected. they are set by the user with the wrsr command and are non ? volatile. the user is allowed to protect a quarter, one half or the entire memory, by setting these bits according to table 9. the protected blocks then become read ? only. the wpen (w rite protect enable) bit acts as an enable for the wp pin. hardware write protection is enabled when the wp pin is low and the wpen bit is 1. this condition prevents writing to the status register and to the block protected sections of memory. while hardware write protection is active, only the non ? block protected memory can be written. hardware write protection is disabled when the wp pin is high or the wpen bit is 0. the wpen bit, wp pin and wel bit combine to either permit or inhibit write operations, as detailed in table 10. the ipl (identification page latch) bit determines whether the additional identification page (ipl = 1) or main memory array (ipl = 0) can be accessed both for read and write operations. the ipl bit is set by the user with the wrsr command and is volatile. the ipl bit is automatically reset after read/write operations. the lip bit is set by the user with the wrsr command and is non ? volatile. when set to 1, the identification page is permanently write protected (locked in read ? only mode). note: the ipl and lip bits cannot be set to 1 using the same wrsr instruction. if the user attempts to set (?1?) both the ipl and lip bit in the same time, these bits cannot be written and therefore they will remain unchanged. table 8. status register 7 6 5 4 3 2 1 0 wpen ipl 0 lip bp1 bp0 wel rdy table 9. block protection bits status register bits array address protected protection bp1 bp0 0 0 none no protection 0 1 18000h ? 1ffffh quarter array protection 1 0 10000h ? 1ffffh half array protection 1 1 00000h ? 1ffffh full array protection table 10. write protect conditions wpen wp wel protected blocks unprotected blocks status register 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable
cat25m01 http://onsemi.com 6 write operations the cat25m01 device powers up into a write disable state. the device contains a write enable latch (wel) which must be set before attempting to write to the memory array or to the status register. in addition, the address of the memory location(s) to be written must be outside the protected area, as defined by bp0 and bp1 bits from the status register. write enable and write disable the internal write enable latch and the correspon?ding status register wel bit are set by sending the wren instruction to the ca t25m01. care must be taken to take the cs input high after the wren instruction, as otherwise the write enable latch will not be properly set. wren timing is illustrated in figure 3. the wren instruction must be sent prior any write or wrsr instruction. the internal write enable latch is reset by sending the wrdi instruction as shown in figure 4. disabling write operations by resetting the wel bit, will protect the device against inadvertent writes. figure 3. wren timing sck si so 00000 110 high impedance note: dashed line = mode (1, 1) cs figure 4. wrdi timing sck si so 00000 100 high impedance note: dashed line = mode (1, 1) cs
cat25m01 http://onsemi.com 7 byte write once the wel bit is set, the user may execute a write sequence, by sending a write instruction, a 24 ? bit address and a data byte as shown in figure 5. only 17 significant address bits are used by the cat25m01. the rest are don?t care bits, as shown in table 11. internal programming will start after the low to high cs transition. during an internal write cycle, all commands, except for rdsr (read status register) will be ignored. the rdy bit will indicate if the internal write cycle is in progress (rdy high), or the device is ready to accept commands (rdy low). page write after sending the first data byte to the cat25m01, the host may continue sending data, up to a total of 256 bytes, according to timing shown in figure 6. after each data byte, the lower order address bits are automatically incremented, while the higher order address bits (page address) remain unchanged. if during this process the end of page is exceeded, then loading will ?roll over? to the first byte in the page, thus possibly overwriting previoualy loaded data. following completion of the write cycle, the cat25m01 is automatically returned to the write disable state. write identification page the additional 256 ? byte identification page (ip) can be written with user data using the same write commands sequence as used for page write to the main memory array (figure 6). the ipl bit from the status register must be set (ipl = 1) using the wrsr instruction, before attempting to write to the ip. the address bits [a23:a8] are don?t care and the [a7:a0] bits define the byte address within the identification page. in addition, the byte address must point to a location outside the protected area defined by the bp1, bp0 bits from the status register. when the full memory array is write protected (bp1, bp0 = 1,1), the write instruction to the ip is not accepted and not executed. also, the write to the ip is not accepted if the lip bit from the status register is set to 1 (the page is locked in read ? only mode). table 11. byte address device address significant bits address don?t care bits # address clock pulses main memory array a16 ? a0 a23 ? a17 24 identification page a7 ? a0 a23 ? a8 24 figure 5. byte write timing sck si so 00 00 00 10 d7 d6 d5 d4 d3 d2 d1 d0 0 1 2 3 4 5 6 7 8 2930313233343536373839 opcode data in high impedance byte address* note: dashed line = mode (1, 1) * please check the byte address table (table 11) cs a n a 0 figure 6. page write timing note: dashed line = mode (1, 1) sck si so 00 00 00 10 byte address* data byte 1 012345678 29303132 ? 39 40 ? 47 data byte 2 data byte n opcode 7..1 0 32+(n ? 1)x8 ? 1....32+(n ? 1)x8 32+nx8 ? 1 data in high impedance cs a n a 0 * please check the byte address table (table 11)
cat25m01 http://onsemi.com 8 write status register the status register is written by sending a wrsr instruction according to timing shown in figure 7. only bits 2, 3, 4, 6 and 7 can be written using the wrsr command. write protection the write protect (wp ) pin can be used to protect the block protect bits bp0 and bp1 against being inadvertently altered. when wp is low and the wpen bit is set to ?1?, write operations to the status register are inhibited. wp going low while cs is still low will interrupt a write to the status register. if the internal write cycle has already been initiated, wp going low will have no effect on any write operation to the status register. the wp pin function is blocked when the wpen bit is set to ?0?. the wp input timing is shown in figure 8. 01 23 45678 10 911121314 sck si msb high impedance data in 15 so 7 6 5 4 3 2 10 0000000 1 opcode figure 7. wrsr timing note: dashed line = mode (1, 1) cs figure 8. wp timing note: dashed line = mode (1, 1) sck wp cs wp t wph t wps
cat25m01 http://onsemi.com 9 read operations read from memory array to read from memory, the host sends a read instruction followed by a 24 ? bit address (see table 11 for the number of significant address bits). after receiving the last address bit, the cat25m01 will respond by shifting out data on the so pin (as shown in figure 9). sequentially stored data can be read out by simply continuing to run the clock. the internal address pointer is automatically incremented to the next higher address as data is shifted out. after reaching the highest memory address, the address counter ?rolls over? to the lowest memory address, and the read cycle can be continued indefinitely. the read operation is terminated by taking cs high. read identification page reading the additional 256 ? byte identification page (ip) is achieved using the same read command sequence as used for read from main memory array (figure 9). the ipl bit from the status register must be set (ipl = 1) before attempting to read from the ip. the [a7:a0] are the address significant bits that point to the data byte shifted out on the so pin. if the cs continues to be held low, the internal address register defined by [a7:a0] bits is automatically incremented and the next data byte from the ip is shifted out. the byte address must not exceed the 256 ? byte page boundary. read status register to read the status register, the host simply sends a rdsr command. after receiving the last bit of the command, the cat25m01 will shift out the contents of the status register on the so pin (figure 10). the status register may be read at any time, including during an internal write cycle. sck si so 000000 11 byte address* 0 1 2 3 4 5 6 7 8 9 10 2829303132333435363738 7 6 5 4 3 2 1 0 data out msb high impedance opcode figure 9. read timing note: dashed line = mode (1, 1) * please check the byte address table (table 11). cs a n a 0 01 2345678 10 911121314 sck si data out msb high impedance opcode so 7 6 5 4 3 2 1 0 00 0 00 101 note: dashed line = mode (1, 1) figure 10. rdsr timing cs
cat25m01 http://onsemi.com 10 hold operation the hold input can be used to pause communication between host and cat25m01. to pause, hold must be taken low while sck is low (figure 11). during the hold condition the device must remain selected (cs low). during the pause, the data output pin (so) is tri ? stated (high impedance) and si transitions are ignored. to resume communication, hold must be taken high while sck is low. design considerations the cat25m01 device incorporates power ? on reset (por) circuitry which protects the internal logic against powering up in the wrong state. the device will power up into standby mode after v cc exceeds the por trigger level and will power down into reset mode when v cc drops below the por trigger level. this bi ? directional por behavior protects the device against ?brown ? out? failure following a temporary loss of power. the cat25m01 device powers up in a write disable state and in a low power standby mode. a wren instruction must be issued prior any writes to the device. after power up, the cs pin must be brought low to enter a ready state and receive an instruction. after a successful byte/page write or status register write, the device goes into a write disable mode. the cs input must be set high after the proper number of clock cycles to start the internal write cycle. access to the memory array during an internal write cycle is ignored and programming is continued. any invalid op ? code will be ignored and the serial output pin (so) will remain in the high impedance state. sck so high impedance figure 11. hold timing t lz hold cs t cd t hd t hd t cd t hz note: dashed line = mode (1, 1)
cat25m01 http://onsemi.com 11 package dimensions soic 8, 150 mils case 751bd ? 01 issue o e1 e a a1 h l c e b d pin # 1 identification top view side view end view notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.33 0.19 0.25 4.80 5.80 3.80 1.27 bsc 1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 l 0.40 1.27 1.35
cat25m01 http://onsemi.com 12 package dimensions soic ? 8, 208 mils case 751be ? 01 issue o e1 eb side view top view e d pin#1 identification end view a1 a l c notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with eiaj edr-7320. symbol min nom max a a1 b c d e e1 e 0o 8o 0.05 0.36 0.19 5.13 7.75 5.13 1.27 bsc 2.03 0.25 0.48 0.25 5.33 8.26 5.38 l 0.51 0.76
cat25m01 http://onsemi.com 13 package dimensions tssop8, 4.4x3 case 948al ? 01 issue o e1 e a2 a1 e b d c a top view side view end view 1 l1 l notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30 0.65 bsc 1.00 ref 1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40
cat25m01 http://onsemi.com 14 ordering information (note 10) device order number specific device marking package type temperature range lead finish shipping (note 11) cat25m01vi ? gt3 25m01a soic ? 8, jedec i = industrial ( ? 40 c to +85 c) nipdau tape & reel, 3,000 units / reel cat25m01ve ? gt3 25m01a soic ? 8, jedec e = extended ( ? 40 c to +125 c) nipdau tape & reel, 3,000 units / reel cat25m01xi ? t2 25m01a soic ? 8, eiaj i = industrial ( ? 40 c to +85 c) matte ? tin tape & reel, 2,000 units / reel cat25m01yi ? gt3 sm1a tssop ? 8 i = industrial ( ? 40 c to +85 c) nipdau tape & reel, 3,000 units / reel cat25m01ye ? gt3 sm1a tssop ? 8 e = extended ( ? 40 c to +125 c) nipdau tape & reel, 3,000 units / reel 10. for additional package and temperature options, please contact your nearest on semiconductor sales office. 11. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 cat25m01/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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